Senior Digital Verification Engineer - 12+ Months - Hybrid

Global Enterprise Partners is seeking a Senior Design Verification Engineer to join a cutting-edge wireless interface initiative. This role focuses on pre-silicon verification of IP modules, subsystems, and SoC designs - not physical design or layout. You'll work cross-functionally to ensure robust, high-quality silicon before tape-out.

Requirements for Senior Design Verification Engineer role :

• 8-12 years of experience in semiconductor design / verification.
• Strong expertise in SystemVerilog, UVM, and C / C++ for testbench development.
• Deep understanding of SoC architecture and pre-silicon verification methodologies.
• Proficient in simulation, debugging, and coverage analysis.
• Skilled in Scripting (Python, Perl, TCL) for automation and tooling.
• Experience with RTL, gate-level, power-aware simulations, and emulation platforms.
• Excellent communication skills for global team collaboration.

Details for Senior Design Verification Engineer role :

Interested?

If you or someone you know is interested in the Senior Design Verification Engineer position, please get in touch with Angelos Gkelmpesis of Global Enterprise Partners

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