Analog IC Physical Design Engineer – Layout, Floorplanning & Tape-out

Vacancy : Analog IC Physical Design Engineer – Layout, Floorplanning & Tape-out

Location : Nijmegen & Eindhoven, Netherlands

Are you an experienced analog layout engineer with strong Cadence skills, looking to focus on physical implementation rather than schematic design ? Then we’ve got a great opportunity for you.

Our client is looking for a specialist to take ownership of the full physical integration of analog ICs – from floorplanning and placement to DRC / LVS and tape-out . You’ll be part of an international team of ~50 physical designers across the Netherlands, Sweden, and India.

What you’ll do

• Take full responsibility for delivering a fully verified physical design
• Independently perform floorplanning, placement, routing, verification, and finishing
• Work in a Cadence Virtuoso (schematic-driven) layout environment
• Lead (junior) physical designers within your project scope
• Document, review, and ensure quality throughout the full layout-to-tape-out flow
• Contribute to knowledge sharing, methodology improvements, and documentation

What you bring

What makes this role different from a standard IC design job?

No transistor-level schematic design – you work directly on the physical layer , closely aligned with circuit designers

No digital SoC work – this is pure analog physical integration

You own the final and most critical phase : tape-out

Interested or know someone who would be a perfect fit? Send them this vacancy and make them apply.