Senior Digital Verification Engineer (8+ years exp) - Eindhoven, Netherlands - Contract

Senior Digital Verification Engineer (8+ years exp)

Initial 12 month contract + possible extensions

Eindhoven, Netherlands (3 days onsite / 2 days remote)

Candidate must be living in the Netherlands currently

Our client :

Enables a smarter, safer and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, our client is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.

Project Details :

Omega Project - development of a Wireless Interface, new project with around 30 team members

Overview :

Perform semiconductor design engineering assignments including engineering and designing chip layout circuits, circuit checking, documenting specifications, modifying and evaluating semiconductor devices and components. Reviews product requirements and logic diagrams for device definition. Typically responsible for projects, or portions of projects, to design, verify, modify, and evaluate semiconductor devices and components. Develops, modifies and evaluates electronic parts, components or integrated circuitry for hardware and other systems. Conducts experimental tests on equipment and evaluates results. Develops specifications for selecting components and equipment to use. May also review vendors’ abilities to support development. Emphasis on Design Verification.

Job Responsibilities :

• Responsible for the pre-silicon verification of IP modules, IP subsystems, and / or SoC top.
• Responsible for defining digital verification strategy and plan for SoC top or its sub-modules.
• Interface to HW, FW, and SW design teams, as well as to architecture and system engineering teams, to understand functionality and application of the IP subsystem, SoC system.
• Responsible for executing verification plan according to the product specification and verification requirements defined by product architects.
• Responsible for developing, debugging and running C / C++, System Verilog or UVM based verification environment for RTL / netlist simulation.
• Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code / functional coverage.

Job Qualifications :

Recruitment process :

2 technical rounds, 1 non-technical