RTL Design Engineer

Our client is a fast-growing Semiconductor start-up, who are seeking a highly skilled RTL Design Engineer with experience in FPGA and / or ASIC development to join their team. This role involves designing and implementing high-performance digital systems, collaborating with cross-functional teams, and contributing to cutting-edge hardware solutions.

Responsibilities :

• Develop RTL designs for FPGA and ASIC applications using Verilog (or VHDL).
• Translate system-level specifications into efficient, scalable digital architectures.
• Optimize designs for timing, power, and area through synthesis and place-and-route using tools like Xilinx Vivado.
• Ensure design closure and compliance with performance constraints via detailed post-synthesis and post-route analysis.
• Apply RTL design best practices including modular design, code reuse, and pipelining techniques.
• Collaborate closely with hardware, software, and system engineering teams to define and integrate FPGA / ASIC requirements.
• Maintain clear and comprehensive documentation for RTL designs, specifications, and user guides.
• Provide project updates, monitor progress against milestones, and proactively highlight risks or issues.
• Stay abreast of industry trends, tools, and technologies in FPGA / ASIC development and evaluate new solutions for ongoing and future projects.
• UVM experience is a plus.

Required Qualifications :