I am partnered with a cutting edge team based in Delft (Netherlands), who specialise in silicon-based micro-electromechanical systems (MEMS) timing solutions.
Please note :
- This is an onsite position in the Netherlands
- Relocation from within Europe can be supported
- Visa sponsorship from outside Europe is not possible
Responsibilities :
Develop micro-architecture specifications for logic circuits based on the Product Requirement Document (PRD).Create RTL designs using Verilog or SystemVerilog.Define timing constraints and clock settings for synthesis and placement tools.Run synthesis tools (e.g., Genus, Design Compiler) and resolve timing issues.Optimize design tradeoffs (timing, area, power).Analyze Static Timing Analysis (STA) reports from tools like Prime Time.Collaborate with cross-functional teams, including analog, verification, backend, system, and test engineering.Perform post-silicon bring-up, validation, and debugging.Requirements :
5+ years of front-end digital design experienceExperience with low power design flowProficiency with RTL design in Verilog / SystemVerilog.Excellent English written and verbal communication skillsSeniority level
Mid-Senior level
Employment type
Full-time
Job function
Semiconductor Manufacturing
J-18808-Ljbffr