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Senior ASIC Verification Engineer

microTECH Global LtdNE, Netherlands

30+ dagen geleden

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Job title : Senior ASIC Verification Engineer

Location : Netherlands

Contract : Permanent

About the client

Our client is a premier chip and silicon IP provider, is seeking to hire an exceptional Senior ASIC Verification Engineer to join our Security team in Rotterdam. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

As a Senior ASIC Verification Engineer, the candidate will be reporting to SPE Verification Engineering and is a Full Time position. This engineer will participate in the verification of secure ASIC cores developers, working with cross functional teams including ASIC design engineers and architects, other verification engineers and system test engineers, security experts, and cryptographers. Cryptography and hardware security experience is not required, but an ability to, and interest in, learning about these areas is important.

Responsibilities

Partner closely with our architecture and design teams in specification and customer requirement reviews
Design and implement verification test plans, testbenches, infrastructure, and platforms to produce thoroughly

verified and robust products

Implement best verification practices and improve on the existing methodologies and flows

Tackle sophisticated problems and develop scalable solutions that work across platforms

Assist with all hardware project phases – bring-up, testing, debug, coverage analysis, and tracking

Qualifications

BS or MS degree in electrical or computer engineering or closely related degree strongly preferred; but

substantial, relevant, outstanding work experience may substitute in some cases

Six or more years of experience working as a verification engineer or related field

Strong written and verbal communication skills : ability to explain complex concepts in front of technical

audience

Strong desire to take ownership of all verification aspects of a project

Exposure to block-level and / or system-level verification

High technical competence that includes a track record of effective verification of complex digital designs

Solid understanding of standard ASIC verification techniques, including :

o Test planning

o Testbench creation

o Code and functional coverage

o Directed and SystemVerilog-based constrained random stimulus generation

o Self-checking – scoreboards, predictors, or reference models

o Assertions

Solid understanding of verification methodologies (UVM or OVM) and standard testbench languages

Comfortable with Unix development environments (make, scripting, SVN, etc.)

Ability to support testbench lint / rule checking, profiling and automation using perl or python scripting

Familiarity with advanced verification techniques such as object-oriented testbenches and formal verification

Beneficial Experience :

Experience developing object-oriented testbench infrastructure in C / C++, OVM, or UVM

Experience in creating FPGA bitfiles for FPGA emulation / acceleration purposes

Familiarity with IP integration, IP core delivery, and handoff issues

Data, software, and / or network security; cryptography

Ability to work with technical writers in the production of technical documentation