DFT Engineer

is a technology company. We believe the camera presents the greatest opportunity to improve the way people live and communicate. Snap contributes to human progress by empowering people to express themselves, live in the moment, learn about the world, and have fun together. The Company’s three core products are , a visual messaging app that enhances your relationships with friends, family, and the world; , an augmented reality platform that powers AR across Snapchat and other services; and its AR glasses, .

Snap Lab is home to our hardware products with a world-class research & development team. We are focused on pushing the boundaries of what a camera can be, specifically overlaying computing on the real world. Next Generation are our first pair of glasses that bring augmented reality to life.

You will be responsible for design for test strategy and implementation in close collaboration with the design and verification teams. You will be part of a highly diverse international team of skilled engineers and scientists, and you are expected to be a key driver of the team’s further growth.

What you’ll do:

• Define the DFT architecture of our state-of-the-art artificial intelligence ASICs for wearable devices that lead to exciting launches of hardware at Snap
• Interface with our third party partner to lead the implementation of the DFT structures
• Participate in the implementation of critical parts of the testing of the chip: MBIST, analog IP testing, SCAN, boundary scan, etc.
• Participate/lead the generation of the patterns for production / qualification
• Interface with our OSAT partner for porting the patterns on the tester
• Define strategy to test the pattern in house
• Participate in the silicon characterisation and qualification plan together with our NPI engineering team.
• Support yield enhancement during the ramp-up of the product
  

Knowledge, Skills & Abilities:

• Hands-on experience with SCAN insertion, including compression
• Hands on experience with MBIST insertion, including repair
• Hands on experience with boundary scan insertion
• Proven experience with testability of chips with low power structure (power switches, retention FF, level shifters, etc).
• Experience with pattern conversion or supporting third parties in converting patterns to a tester.
• Experience with testing high speed interfaces such as MIPI, PCIe or similar.
• Experience with analysis of yield and debugging issues on silicon linked to DFT and yield improvements.
• Proven experience in process development and documentation
• Excellent written and verbal English communication
  

Minimum Qualifications:

• MSc degree in related field such as electrical engineering or equivalent years of experience
• 7+ years of experience in Design for test implementation.
  

Preferred Qualifications:

• Design for test in the broadest sense
• Knowledge of ASIC production flow
• Experience of at least one product managed successfully through production in volume
• Ideal candidate is a self-starter, can organize complex issues and drive them to closure
• Candidate is able to multitask and prioritize.
• Experience with common requirement management practices, software engineering tools such as Gitlab, etc.
• A passion for Snapchat and creativity!