Radar Design FPGA Engineer

KRUSH Labs is developing cutting-edge wireless communication and sensing systems that push the boundaries of performance and reliability. Our technologies address a spectrum of modern sensing and communication systems needs including long-range sensing and communication, high resolution sensing, high data rates, low latency, interference robustness and resilience to multipath. This creates unique opportunities to research, design, and implement next-generation radio and radar systems.

We are looking for an experienced Radar Design FPGA Engineer to join our dynamic team. In this role, you will be responsible for developing and maintaining robust FPGA based software/hardware codesign and verification flows. , while defining strategies to ensure the performance, quality, and reliability of our FPGA-based systems. You will work on software/hardware co-design solutions and contribute to cutting-edge radar development projects. Leveraging your expertise in Verilog/SystemVerilog, FPGA/VLSI design, and modern verification methodologies such as Cocotb, you will help deliver high-quality solutions from concept through deployment.

As part of this role, you will be a member of the broader FPGA and verification community within KRUSH Labs, collaborating with experienced engineers to continuously improve our design, verification, and development methodologies.

Key Responsibilities

• Maintain a clean, scalable, and portable software/hardware co-design and build environment.
• Develop lint-clean RTL modules based on system-level and algorithmic specifications.
• Integrate third-party IP blocks and ensure correct functionality within FPGA-based systems.
• Review and refine system designs, including software and RTL implementations, to ensure high code quality and complete functional coverage.
• Contribute to the enhancement of internal FPGA design, verification, and testing methodologies.
• Develop and maintain verification environments using modern methodologies and tools such as Cocotb.
• Debug timing issues and contribute to timing closure during static timing analysis (STA).
• Perform board-level debugging using logic analyzers and related hardware validation tools.
• Collaborate closely with algorithm, software, and systems engineers to translate requirements into robust FPGA implementations.
• Participate in laboratory and field testing activities to validate system performance in real-world environments.

Requirements

Technical Qualifications Required

• 5+ years of experience in FPGA or front-end VLSI design and verification.
• At least 1 year of experience with Petalinux and/or bare-metal software bring-up.
• Master's degree in Electrical Engineering, Electronic Engineering, Computer Engineering, or a related field.
• Strong working knowledge of C/C++ and Python.
• Experience with structured, lint-clean RTL development using Verilog and/or SystemVerilog.
• Familiarity with verification methodologies and frameworks such as Cocotb.
• Experience implementing hardware accelerators on FPGA platforms.
• Basic understanding of digital communication systems theory.
• Experience implementing fixed-point DSP algorithms in RTL is considered an advantage.

Nice to Have

• Understanding of wireless communication and signal processing concepts such as MIMO, OFDM, beamforming, or channel estimation.
• Experience with radar systems, including radar signal processing or radar FPGA implementations.
• Experience with Xilinx/AMD FPGA development tools and workflows.
• Familiarity with embedded Linux environments and heterogeneous SoC platforms.

Required Skills and Abilities

• Strong analytical and problem-solving skills with a proactive, hands-on approach.
• Excellent communication and collaboration skills, with the ability to work effectively across multidisciplinary teams.
• Strong attention to detail and commitment to delivering high-quality, reliable designs.
• Passion for innovation and continuous improvement of FPGA design and verification methodologies.
• Ability to work independently while contributing positively to a collaborative engineering culture.