Senior Digital ASIC Design Engineer

Position: Senior Digital ASIC Design Engineer
Location: Delft, Amsterdam


About the company:
A start-up company on a mission to conquer the high-power consumption challenges in Global Navigation Satellite Systems and IoT sensors. The vision is to revolutionize radio chip technology.
The team is currently built of 30 individuals, scaling to 40 in the next year.
This isn’t just about a job, it's about embracing high standards and boldly navigating unexpected challenges.

Key responsibilities:
•You will be responsible for the simulation and verification of digital block implemented in RTL for various functions including control state machine digital signal processing (DSP), and multiple clock domain interface management
•Post-layout simulation of complex mixed-signal SOC
•You will develop test benches and test cases for block-level functional verification
•Work with backend/implementation teams to address synthesis, timing, DFT issues for ASIC implementation
•Define verification and test plan, run regressions, reproduce, and debug functional and performance bugs.
•Collaborate with analog design engineers, CAD, systems engineering, test engineering and applications teams to ensure define optimal DFT, DFM features and achieve rapid silicon bring-up and time to production release
•Analyze circuit for failure root cause analysis, investigate anomalous observations in silicon across various conditions, including PVT variations, and propose solutions
•Verification of various IPs/Sub IPs integrated to top level SoC

Requirements:
Senior Digital ASIC Design Engineer who thrives in an environment where your proactive and can-do attitude, is highly appreciated. The ideal candidate for this role must have:
•5+ years of experience in ASIC verification, System Verilog, UVM, Verilog.
•Proficiency with EDA tools (Candence, Mentor) and design languages including Verilog
•You understand all design integration activities like Lint, CDC, Synthesis & ECO
•Experience in designing complex mixed-signal products containing analog building blocks, and microcontrollers etc.
•Experience with RTL and ultra-low-power designs
•Good knowledge of digital design flow from architecture design to sign-off
•Understanding of synthesis, static timing analysis, and netlist verifications
•Understanding of digital backend flow for Floor Planning and Place & Route (PNR)
•Understanding of digital DFT/ECO flow
•Understanding of backend design flow, including RTL synthesis, clock tree synthesis, scan and DFT insertion, place and route, and netlist verification
•Strong programming and scripting skills: MATLAB, C/C++, Tcl
•Experience in setting up Power Distribution architecture, power intent specification and validation methodology.
•Strong knowledge of clock domain crossing (CDC) techniques.
•Understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level simulation
•Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation
•Strong analytical, problem-solving skills.
•Ability to work effectively in a fast-moving and dynamic environment.
•Experience working with standards including ARM AMBA APB, AHB, AXI bus based SOCs is desirable.
•Good knowledge MCU peripherals (SPI, I2C, GPIO, ADC, Non-Volatile Memory, etc.) is a plus.

Further benefits:
•All employees will be provided with Stock Appreciation Rights. You'll financially profit from the companies success.
•Pension: an extra 2% of your monthly base salary.
•25 vacation days based on a 40-hour work-week.
•Work in a beautiful & modern office with all the necessary equipment you need to deliver a great job.
•Quarterly social events such as meals, playing VR games, bowling, etc
•Monthly “Lunch & Learn” sessions to keep you up to speed


If you are interested please